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| comment | | "parent_author":"",<br>"parent_permlink":"technology",<br>"author":"salah-g",<br>"permlink":"samsung-now-mass-producing-industry-s-first-2nd-generation-10-nanometer-class-dram",<br>"title":"Samsung Now Mass Producing Industry\u2019s First 2nd-Generation,<br> 10-Nanometer Class DRAM",<br>"body":"![ (https:\/\/steemitimages.com\/DQmfFG9kskRK1jXjCfNg96REkYsSJR7HdPiFWD1b9G8QZ5L\/image.png)\n\nSEOUL,<br> South Korea,<br> Dec. 20,<br> 2017 \u2014 Samsung Electronics Co.,<br> Ltd.,<br> a world leader in advanced memory technology,<br> announced today that it has begun mass producing the industry\u2019s first 2nd-generation of 10-nanometer class* (1y-nm),<br> 8-gigabit (Gb) DDR4 DRAM. For use in a wide range of next-generation computing systems,<br> the new 8Gb DDR4 features the highest performance and energy efficiency for an 8Gb DRAM chip,<br> as well as the smallest dimensions.\n\n\n\u201cBy developing innovative technologies in DRAM circuit design and process,<br> we have broken through what has been a major barrier for DRAM scalability,<br>\u201d said Gyoyoung Jin,<br> president of Memory Business at Samsung Electronics. \u201cThrough a rapid ramp-up of the 2nd-generation 10nm-class DRAM,<br> we will expand our overall 10nm-class DRAM production more aggressively,<br> in order to accommodate strong market demand and continue to strengthen our business competitiveness.\u201d\n\nSamsung\u2019s 2nd-generation 10nm-class 8Gb DDR4 features an approximate 30 percent productivity gain over the company\u2019s 1st-generation 10nm-class 8Gb DDR4. In addition,<br> the new 8Gb DDR4\u2019s performance levels and energy efficiency have been improved about 10 and 15 percent respectively,<br> thanks to the use of an advanced,<br> proprietary circuit design technology. The new 8Gb DDR4 can operate at 3,<br>600 megabits per second (Mbps) per pin,<br> compared to 3,<br>200 Mbps of the company\u2019s 1x-nm 8Gb DDR4.\n\nTo enable these achievements,<br> Samsung has applied new technologies,<br> without the use of an EUV process. The innovation here includes use of a high-sensitivity cell data sensing system and a progressive \u201cair spacer\u201d scheme.\n\nIn the cells of Samsung\u2019s 2nd-generation 10nm-class DRAM,<br> a newly devised data sensing system enables a more accurate determination of the data stored in each cell,<br> which leads to a significant increase in the level of circuit integration and manufacturing productivity.\n\nThe new 10nm-class DRAM also makes use of a unique air spacer that has been placed around its bit lines to dramatically decrease parasitic capacitance**. Use of the air spacer enables not only a higher level of scaling,<br> but also rapid cell operation.\n\nWith these advancements,<br> Samsung is now accelerating its plans for much faster introductions of next-generation DRAM chips and systems,<br> including DDR5,<br> HBM3,<br> LPDDR5 and GDDR6,<br> for use in enterprise servers,<br> mobile devices,<br> supercomputers,<br> HPC systems and high-speed graphics cards.\n\nSamsung has finished validating its 2nd-generation 10nm-class DDR4 modules with CPU manufacturers,<br> and next plans to work closely with its global IT customers in the development of more efficient next-generation computing systems.\n\nIn addition,<br> the world\u2019s leading DRAM producer expects to not only rapidly increase the production volume of the 2nd-generation 10nm-class DRAM lineups,<br> but also to manufacture more of its mainstream 1st-generation 10nm-class DRAM,<br> which together will meet the growing demands for DRAM in premium electronic systems worldwide.",<br>"json_metadata":" \"tags\":[\"technology\" ,<br>\"image\":[\"https:\/\/steemitimages.com\/DQmfFG9kskRK1jXjCfNg96REkYsSJR7HdPiFWD1b9G8QZ5L\/image.png\" ,<br>\"app\":\"steemit\/0.1\",<br>\"format\":\"markdown\" " | | vote | "voter":"salah-g",
"author":"salah-g",
"permlink":"samsung-now-mass-producing-industry-s-first-2nd-generation-10-nanometer-class-dram",
"weight":10000 |
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